I2C Communication Protocol, Bus and Interface

In this blog post, you will learn about the I2C protocol, the working of the I2C Communication protocol, hardware bus configuration, and how data is transferred in I2C communication with its uses in chip-to-chip communication. I will also explain the terms which frequently used in the I2C protocol. So, let’s begin the post with an introduction to the I2C protocol.

I2C Protocol Introduction:

An I2C protocol is one of the serial communication protocols that is used for the chip-to-chip communication. Similar to the I2C protocol, SPI and UART also used for the chip to chip communication.

The I2C is the short form of Inter-Integrated Circuit, is a type of bus, which designed and developed by Philips in 1980 for inter-chip communication.I2C is adopted by a lot of vendor companies for the chip to chip communication.

I2C is a multi-master and multi-slave serial communication protocol means that we have the freedom to attach multiple IC at a time with the same bus. In the I2C protocol, communication is always started by the master and in the case of multi-master, only one master has ownership of the I2C Bus.

“The good point about this blog post is that I will explain each point very slowly and also keep in mind the beginners and fresher who face difficulty in their starting of career. So might be you will face some repetitive sentence I am apologizing for it.”

What is I2C Communication Protocol?

I2C is a serial communication protocol. It provides good support to slow devices, such as EEPROM, ADC, RTC, etc. Using the I2C communication, we can transfer the data between Master (central processor) and slaves (multiple ICs) on the same circuit board through the 2 wires (Databus and clock bus).

Because in I2C we used two wires for the communication so generally, people call it a two-wire communication protocol. One wire is used for the data (SDA) and the other wire is used for the clock (SCL).

You should know that I2C is a half-duplex protocol. It is the reason the buses used in I2C communication are bidirectional. Here bidirectional means, master able to send and receive the data from the slave.

The clock bus is used to control the data transfer and it synchronizes the master and slave together. In communication master and slave share the same clock, it is the reason I2C communication comes in the category of the synchronous serial communication protocol. The clock bus is controlled by the master but in some situations, the slave is also able to suppress the clock signal, but I will discuss it later.

Additionally, an I2C bus is used in various control architectures, for example, SMBus (System Management Bus), PMBus (Power Management Bus), IPMI (Intelligent Platform Management Interface), etc. You’ll probably find yourself using I2C if you ever worked on projects that use I2C LCD, Accelerometer Module, Biometric sensor, OLED displays ..etc.

Why use I2C Protocol

Unlike the serial com port I2C is the synchronous communication, in I2C both master and slave use the shared clock which is produced by the master.

In serial port, both the transmitter and receiver device have their own clock generator. Hence it is very important to minimize the difference between the clock of the transmitter and slave otherwise data will be corrupt during the communication.

Another disadvantage of asynchronous serial com port is that only two devices can transmit and receive the data at a time but besides it, I2C can be multi-master and multi-slave.

Asynchronous serial is used UART chip for the communication. There is no specific limit defined for asynchronous communication but most of the serial devices support up to the maximum baud rate of 230400.

SPI is full-duplex and faster than I2c although sometimes I2C is much easier and beneficial. In I2C, we needed only two wires for the communication but in SPI we needed four-wire for the communication.I2c can be multi-master but SPI never can be multi-master. We have already discussed the difference between I2C and SPI, If you want you can check this article “SPI vs I2C“.

Let’s see some of the important features of the I2C communication protocol:

Feature of I2C Bus:

In I2C only two buses are required for the communication, the serial data bus (SDA) and serial clock bus (SCL).
Each component in the I2C bus is software addressable by a unique address, this unique address is used by the master to communicate with a particular slave.
I2C supports 7-bit and 10-bit addressing structures to target a specific slave (device or IC) on the I2C bus.
Always a master and slave relationships exist at all times in I2C Bus.
In I2C, communication always started by the master by sending the start bit.
During the communication, we get the acknowledgment bit after each byte.
The I2C bus provides the ability of arbitration and collision detection.
I2C is the 8-bit oriented serial bidirectional communication, there are the following speed mode supported by the I2C Bus.

MODE	SPEED
Standard-mode	100 kbit/s
Fast-mode	400 kbit/s
Fast-mode Plus	1 Mbit/s
High-speed mode	3.4 Mbit/s

Note: (Unidirectional bus) -> Ultra Fast-mode (UFm), with a bit rate up to 5 Mbit/s.

I2C Bus Physical layer:

As we know I2C is a pure master and slave communication protocol and can be a multi-master or multi-slave. But we generally see a single master with multi slave in I2C communication.

I2C Bus consists of only two wires and is named serial data line (SDA) and a serial clock line (SCL). At the physical layer, both SCL and SDA lines are of the open-drain design, thus pull-up resistors are needed. High-speed systems (and some others) may use a current source instead of a resistor to pull up only SCL or both SCL and SDA, to accommodate higher bus capacitance and enable faster rise times.

The SDA wire is used to transfer the data and the SCL wire is used to synchronize the master and slave with the clock signal. See the below image in which all the slave devices and master are connected to the same SCL and SDA lines in the I2C network.

Because all slave and master are connected with the same data and clock bus, here important point needs to remember that these buses are connected using the WIRE-AND configuration which is done by putting both wires in an open drain design. The wire-AND configuration allows in I2C to connect multiple nodes to the bus without any short circuits from signal contention.

The open-drain allows the master and slave to drive the line low and release to a high impedance state. So In that situation, when the master and slave release the bus, need a pull resistor to pull the line high. The value of the pull-up resistor is very important because the incorrect value of the pull-up resistor can be lead to signal loss.

A low value of a pull-up resistor is called a strong pull-up resistor (more current flows) and a high resistor value is called a weak pull-up resistor (less current flows).

Note: We know that the I2c communication protocol supports multiple masters and multiple slaves. But most system designs include only one master and in the case of a multi-master, only a single master stays active on the I2C bus at a time.

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Working of I2C protocol

I2C is a simple chip-to-chip communication protocol. In I2C, communication is always started by the master. When the master wants to communicate with the slave then it asserts a start bit followed by the slave address with read/write bit.

After the asserting of the start bit, all slave comes in the attentive mode. If the transmitted address match with any of the slaves on the I2C Bus then an ACKNOWLEDGEMENT (ACK) bit is sent by the slave to the master.

After getting the ACK bit, the master starts the communication. If there is no slave whose address matches the transmitted address then the master received a NOT-ACKNOWLEDGEMENT (NACK) bit, in that situation either master asserts the stop bit to stop the communication or asserts a repeated start bit on the line for new communication.

Data Frame overview of I2C protocol

I2C is an eight-bit communication protocol and an ACK or NACK bit associated with each byte. In I2C data is transferred in messages. An I2C transaction may consist of multiple messages. Each message begins with a start bit, and the transaction ends with a stop bit. Master may send another start condition to retain control of the bus for another message (a “combined format” transaction).

Messages are broken up into frames of data. Each message has an address frame (slave address), and one or more data frames that contain the data being transmitted. The message also consists of read/write bits, ACK/NACK bits between each data frame. See the below Image,

Below I am going to describe each part of the I2C data frame which helps you to understand the I2C message format.

Start Condition

The default state of the SDA and SCL line is high (Due to the pull-up resistors). A master asserts the start condition on the line to start the communication. “A high to low transition of the SDA line while the SCL line is high called the Start Condition“.

In simple words, you can understand that whenever a master decides to start a communication, it switches the SDA line from high voltage level to a low voltage level before the SCL line switches from high to low. You can see the below image.

You should remember that the Start Condition is always asserted by the master and the I2C bus is considered busy after the assertion of the START bit.

Stop Condition

The STOP condition is asserted by the master to stop communication. “A Low to high transition of the SDA line while the SCL line is high called the STOP condition“. Whenever a master decides to stop communication, it switches the SDA line from low voltage level to high voltage level before the SCL line switches from high to low. See the below image.

The STOP condition is always asserted by the master. The I2C bus is considered free after the assertion of the STOP bit.

Note: A START and STOP condition is always asserted by the master.

Repeated Start Condition

The Repeated Start Condition is similar to the Start Condition but both have different meanings. The Repeated Start is asserted by the master before the stop condition (When the bus is not in an idle state).

The I2C Bus is considered busy between each start and stop condition. If the master tries to initiate a new transfer and does not want to lose control over the I2C Bus before starting the new transfer, then it issues a new Start Condition. This asserted start condition is called a Repeated Start Condition.

The repeated start is beneficial for the master when it wants to start a new communication without asserting the stop condition.

Note: Repeated start is beneficial when more than one master is connected with the I2c Bus.

Address Frame

Like SPI, I2C doesn’t have the slave select lines to select the appropriate slave device for communication. It uses an addressing mechanism to select the appropriate slave device. It is also the reason some people call It, address base bus protocol.

So you have to send the address of the slave followed by the Start bit for the communication. The address frame is always the first frame of the message. I2C supports 7-bit and 10-bit addressing structures. Let’s see a message for the 7-bit addressing structure,

Field:

I²C address field

R/W’

I²C message sequences…

Type

Start

Byte 1

ACK

Byte X etc…

Rest of the read or write

message goes here

Stop

Bit position in byte X

7-bit address pos

Note

MSB

LSB

1 = Read

0 = Write

Read/Write Bit

If you will see the above-mentioned message, you will find that the address frame includes a single R/W bit at the end. This bit specifies the direction of data transfer. If the master wants to transfer the data to the slave device, the R/W bit will be ‘0’. Also, if the master wants to receive data from the slave device, the R/W bit will be ‘1’. We will see it in the below read/write operations.

ACK/NACK Bit

If you will see the above-mentioned message, you will find that each frame in a message is followed by an ACK/NACK bit. Basically, it is a protocol overhead, ACK/NACK stands for Acknowledged/Not-Acknowledged bit. The sender will get an ACK bit if an address frame or data frame was successfully received by the receiver in I2C Bus.

Let’s see some scenarios, where NACK bit is generated

When the receiver is unable to receive or transmit the data, in that situation it generates a NACK bit to stop the communication.
During the communication, if the receiver gets any data or commands which are not understood by the receiver then it generates a NACK bit.
During the transfer, if the receiver performs any real-time operation and is not able to communicate with the master then assert a NACK bit.
When the Master is a receiver and reads the data from the slave, then after the reading of the whole data it asserts a NACK bit on data lines to stop the communication.
If there is no device present in the I2c bus of the same address which is transmitted by the master, then the master will not get acknowledged by any slave and treat this situation as NACK.

Byte Format in I2C Protocol (Data Frame)

In I2C, every data which is transmitted over the SDA line must be eight-bit longs. It is very important to remember that in I2C the data bit is always transmitted from the MSB and we can send or receive any number of bytes in I2C between the start and stop conditions.

The sender always gets NACK/ACK bit just after the data frame to verify the frame has been received successfully. You can also say that each data frame is immediately followed by an ACK/NACK bit.

In I2C, one bit is always transmitted on every clock. A byte that is transmitted in I2C could be an address of the device, the address of the register, or data that is written to or read from the slave device.

In I2C, the SDA line is always stable during the high clock phase except for the start condition, stop condition, and repeated start condition. The SDA line only changes its state during the low clock phase.

Note: SDA can only change their state only SCL is low except for the Start Condition, Repeated Start Condition, and Stop Condition.

Handshaking Process in I2C Protocol

In I2C for each byte, an acknowledgment needs to be sent by the receiver, this acknowledgment bit is proof that data is properly received by the receiver and it wants to continue the communication.

A master starts the communication to assert a start condition on the bus. After the start condition master is transmitted a 7-bit address with associated read or write bits ( here I am discussing a 7-bit address).

After the transmission of the address byte, the master releases the data lines to put the data line (SDA) in a high impedance state, which allows the receiver to give the acknowledgment bit.

If this transmitted address is matched with any receiver then it pulls down the SDA lines low for the acknowledgment and after the acknowledgment, it releases the data lines. The master generates a clock pulse to read this acknowledgment bit and continue the read or write operation.

If this transmitted address is not matched with any receiver then nobody is pull down the data lines low, master understands it is a NACK and in that situation, the master asserts a stop bit or repeated start bit for further communication.

I2C write operation

In I2C before performing, the write operation master has to assert a start condition on the I2c bus with the slave’s address and write control bit (for write operation R/W bit will be 0).

If the transmitted address match with any slave device (EEPROM) which connected to the I2C bus then master receives an acknowledge bit. After getting the ACK bit master send the address of the register, where it wishes to write, the slave will acknowledge again, letting the master know it is ready for the write operation.

After getting this acknowledgment, the master will start sending the data to the slave. Master will get the acknowledgment of each transmitted byte.

If the master does not get the acknowledgment from the slave then the master asserts a stop condition to stop the communication or either assert the repeated start to establish a new communication. There or another option to stop the communication when the master has sent all the data then the master is terminated the transmission with a STOP condition.

I2C Read operation

I2C read operation same as the I2C write operation, In which the master asserts the start condition before the read operation. After the start condition master transmit the slave address with read control bit (for read operation R/W bit will be 1), if the transmitted address match with any device in the I2C Bus then it acknowledges to the master to pulling down the data bus(SDA).

After getting the ACK bit, the master releases the data bus but continues sending the clock pulse, in that situation master becomes the receiver and the slave becomes the slave transmitter.

In the read operation, the master gives the acknowledgment to the slave on receiving every byte to let the slave know that it is ready for more data. Once the master has received the number of bytes that it is expecting, it will send a NACK bit to release the bus and assert the stop bit to halt the communication.

Special cases in I2C

There is some special scenario in the I2C protocol, here I am explaining these special scenarios one by one.

Clock synchronization in I2C

Unlike Rs232, I2C is synchronous communication, in which a clock is always generated by the master and this clock is shared by both master and slave. In the case of multi-master, all master generate their own SCL clock, hence the clock of all masters must be synchronized. In the I2C, this clock synchronization is done by wired and logic.

Let’s see an example for a better understanding, where two masters try to communicate with a slave. In that situation, both masters generate their own clock signal, master M1 generates clk1 and master M2 generates clk2, and the clock observed on the bus is SCL.

The SCL clock would be the Anding (clk1 & clk2) of clk1 and clk2 and most interesting thing is that the highest logic 1 of the SCL line defines by the master clock which has the lowest logic 1.

Arbitration in I2C Bus

Arbitration is required in the case of a multi-master, where more than one master is tried to communicate with a slave simultaneously. In I2C arbitration is achieved by the SDA line.

For Example,
Suppose two masters in the I2C bus try to communicate with a slave simultaneously and assert a start condition on the bus. The SCL clock of the I2C bus would be already synchronized by the wired and logic.

In the above case, everything will be good till the state of the SDA line will the same as what is the masters driving on the bus. If any master sees that the state of the SDA line differs, and what is it driving, then they will exit from the communication and lose their arbitration.

Note: Master who is losing their arbitration will wait till the bus become free.

Clock stretching in I2C

Communication in the I2C bus can be paused by the clock stretching to hold the SCL line low and it cannot continue until the SCL line is released high again.

In I2C, the slave able to receive the data at a fast rate but sometimes the slave takes more time in the processing of received data. In that situation, slave pulls the SCL line low to pause the communication and after the processing of the received bytes, it again released the SCL line high to resume the communication.

The clock stretching is how slave drive the SCL line but it is the fact, most of the slave does not drive the SCL line

Note: In the I2c communication protocol, most of the I2C slave devices do not use the clock stretching feature, but every master should support the clock stretching.

Advantages of I2C communication protocol

There is a lot of advantage of the I2C protocol which makes the user helpless to use the I2C protocol in many applications.

It is a synchronous communication protocol, so no need for precise oscillators for the master and slave.
I2C requires only two-wire, one wire for the data (SDA), and the other wire for the clock (SCL).
It provides flexibility to the user to select the transmission rate as per the requirements.
In the I2C bus, each device on the bus is independently addressable.
It follows the master and slave relationships.
It has the capability to handle multiple masters and multiple slaves on the I2C Bus.
I2C has some important features like arbitration, clock synchronization, and clock stretching.
I2C provides ACK/NACK (acknowledgment/ Not-acknowledgement) features that provide help in error handling.

Some important limitations of the I2C communication protocol

An I2C protocol has a lot of advantages but besides it, I2C has a few limitations.

It consumes more power than other serial communication buses due to open-drain topology.
It is good only for a short distance.
I2C protocol has some limitations for the number of slaves. The number of slaves depends on the capacitance of the I2C bus.
It only provides a few limited communication speeds like 100 kbit/s,400 kbit/s, etc.
In I2c, devices can set their communication speed, slower operational devices can delay the operation of faster speed devices.

Conclusion

I2c is an easy and cheap communication protocol, It can be multi-master or multi-slave. In I2c we get the acknowledgment (ACK) and not acknowledgment(NACK) bits after each transmitted byte. Some disadvantage also attaches with I2C, it is a half-duplex communication and slow as compared to SPI (serial peripheral communication).