MCQ On Arm Processor-PART-1: Arm Processor Multiple Choice Questions and Answers

MCQ On Arm Processor-PART-1 with answers and explanations for placement tests and job interviews. These solved Arm Processor MCQ are useful for the campus placement for all freshers including Engineering Students, MCA students, Computer and IT Engineers, etc.

Our Arm Processor MCQ- PART1 ( Arm Processor multiple Choice Questions ) focuses on the basic concept of the ARM processor. We will regularly update the quiz and most interesting thing is that questions come in a random sequence. So every time you will feel new questions.

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MCQ On Arm Processor-PART-1

MCQ On Arm Processor-PART-1: Arm Processor Multiple Choice Questions and Answers

1 / 54

Which among the following is/are integrated by OTG controller in order to implement OTG dual-role device functionality?

Host Controller

Master-only I2C bus interface

Device Controller

All of the above

2 / 54

User Application will run in thread mode if any interrupt or exception event occurs, it will automatically enter in

Remain in thread mode

handler mode

Low power mode

exception mode

None of the above

3 / 54

Abort mode generally enters when _______

low priority interrupt is raised

an attempt access memory fails

ARM processor is on rest

undefined instructions are to be handled

4 / 54

In the branch instructions of ARM, what does the mnemonic BVC imply?

Carry Set

Overflow Set

Carry Clear

Overflow Clear

5 / 54

What is/are the configuration status of the control unit in RISC Processors?

Hardwired

Microprogrammed

Both a and b

None of the above

6 / 54

How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

Faster

Slower

No difference

None of the above

7 / 54

Which microcontrollers are adopted for designing medium-scale embedded systems?

16-bit to 32-bit

8-bit

64-bit

All of the above

8 / 54

In the ARM, PC is implemented using ___________

Caches

Heaps

General purpose register

Stack

9 / 54

RISC stands for _________

Restricted Instruction Sequencing Computer

Reduced Instruction Set Computer

Restricted Instruction Sequential Compiler

Restricted Instruction Set Computer

10 / 54

State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applied. This instruction branches to the initialization code.

True

False

11 / 54

ARM stands for _____________

Advanced Rate Machines

Advanced RISC Machines

Artificial Running Machines

Aviary Running Machines

12 / 54

Both baud rate and bit rate imply the same thing.

True

False

13 / 54

What is the capability of ARM7 f instruction for a second?

115 MIPS

110 MIPS

150 MIPS

130 MIPS

14 / 54

24-bits equals how many bytes?

2.5

15 / 54

The additional duplicate register used in ARM machines are called as _______

Copied-registers

Banked registers

EXtra registers

Extential registers

16 / 54

In Von Neumann architecture, which among the following handles all the operations of the system that are inside and outside the processor?

Memory Unit

Input Unit

Output Unit

Control Unit

17 / 54

The address space in ARM is ___________

2^24

2^64

2^32

2^16

18 / 54

In the ARM Nomenclature ARMxTDMI, D and M stand for

Debug and Fast Multiplier units are present

Division and Multiplier units are present

Debugger and Multiplier units are not present

Division and Multiplier units are not present

19 / 54

What 3 registers make up the Program Status Register (PSR)?

APSR, EPSR, IPSR

APSR, EPSR, R14

APSR, LR, IPSR

LR, PC, SP

20 / 54

In CPU structure, where is one of the operands provided by an accumulator in order to store the result?

Control Unit

Memory Unit

Arithmetic Logic Unit

Output Unit

21 / 54

Which type of handshake packet indicates that the device is incapable of accepting data as it is supposed to be busy with some other task?

ACK

NAK

STALL

None of the above

22 / 54

The offset used in the conditional branching is __________ bit.

23 / 54

In CPU structure, what kind of instruction to be executed is held by an Instruction Register (IR)?

Current (present)

All of the above

24 / 54

Which types of an embedded system involve the coding at a simple level in an embedded 'C', without any necessity of RTOS?

Small Scale Embedded Systems

Medium Scale Embedded Systems

Sophisticated Embedded Systems

All of the above

25 / 54

Where the global variable stored?

RAM

ROM

EEPROM

FLASH

Peripheral location

26 / 54

____ is the processing of instruction broken down to smaller unit

Pipeline

ALU

MCU

All of the above

27 / 54

Application Program Status Register (APSR) access from?

Any processor mode.

privileged mode only

Non privileged mode only

None of the above

28 / 54

While designing an embedded system, which sub-task-oriented process allocates the time steps for various modules that share similar resources?

Simulation and Validation

Iteration

Hardware-Software Partitioning

Scheduling

29 / 54

Is the ARM Cortex-M a microprocessor or a microcontroller?

Microprocessor

Microcontroller

Both

None of the above

30 / 54

The main importance of ARM microprocessors is providing operation with ______

Low cost and low power consumption

Higher degree of multi-tasking

Lower error or glitches

Efficient memory management

31 / 54

If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

12 cycles

4 cycles

6 cycles

9 cycles

32 / 54

Each instruction in ARM machines is encoded into __________ Word.

2 byte

3 byte

4 byte

8 byte

33 / 54

Memory can be accessed in ARM systems by __________ instructions.

Store

MOVE

Load

arithmetic

logical

34 / 54

In the process of pipelining, which instructions are fetched from the memory by the ARM processor during the execution of current instruction?

Present

All of the above

35 / 54

ARM7 has an in-built debugging device?

True

False

36 / 54

If the three stages of execution in pipelining are overlapped, how would be the speed of execution?

Moderate

Lower

Higher

Unpredictable

37 / 54

The ARM processors don’t support Byte addressability.

True

False

38 / 54

Which interrupt controller is present in the Cortex-A15 processor?

Integrated GIC

GIC-390

GIC-500

GIC-400

39 / 54

In the Cortex-A processor series, which among the following is the standalone and smallest processor in size constraints with high-end application support?

Cortex-A5

Cortex-A9

Cortex-A53

Cortex-A59

40 / 54

Which type of branching instructions of thumb possesses 11-bit address & is generally applicable for slightly longer jumps in order to implement the instructions like GOTO of high-level languages?

Short Conditional Branch

Medium Range Unconditional Branch

Long Range Subroutine Calls

None of the above

41 / 54

ARM processors where basically designed for _______

Main frame systems

Distributed systems

Super computers

Mobile systems

42 / 54

The pseudo instruction used to load an address into the register is _________

LOAD

STORE

ASSIGN

ADR

43 / 54

How is the nature of instruction size in CISC processors?

Fixed

Variable

Both a and b

None of the above

44 / 54

In the SPI bus, which signal line carries data from master to slave device & hence regarded as Slave Input/Slave Data In (SI/SDI)?

Master In Slave Out (MISO)

Master Out Slave In (MOSI)

Serial Clock (SCLK)

Slave Select (SS)

45 / 54

The addressing mode where the EA of the operand is the contents of Rn is ______

Pre-indexed mode

Pre-indexed with write back mode

Post-indexed mode

None of the above

46 / 54

Which type of non-privileged processor mode is entered due to the raising of the high priority of an interrupt?

User mode

Interrupt Mode (IRQ)

Fast Interrupt Mode (FIQ)

Supervisor Mode (SVC)

47 / 54

Which parameter/s is/are included in the 'Time to market' design metric of an embedded system?

Time to prototype

Time to refine

Time to produce in bulk

All of the above

48 / 54

The benefits of using thumb instructions are as follows

Low power consumption

High power consumption

Reduction in code memory

Increase in code memory

49 / 54

Microprocessors have all of the following.

CPU, Interrupts, Interface, Ports

RAM, CPU, Interrupts, Interface, Ports

RAM, ROM, CPU, Interrupts, Interface, Ports

None of the above

50 / 54

The address system supported by ARM systems is/are ___________

Little Endian

Big Endian

Both Little & Big Endian

X-Little Endian

51 / 54

Which of the following statements are true with respect to pipelining.
I. Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is not visible to the programmer
II. Each step is called a pipe stage or pipe segment
III. Pipeline machine cycle is the time required to move an instruction one step down the pipeline

All are true

I and III are true

II and III are true

All of the above

52 / 54

In the Cortex-R processor series, which among the following represent/s dual-core configuration along with the space-saving the floating-point unit?

Cortex-R 4

Cortex-R 5

Cortex-R 7

All of the above

53 / 54

An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is called _______.

MRC

MRS

MSR

MCS

54 / 54

What are the profiles for ARM architecture?

A,R

A,R,M

R,M

A,M

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