MCQ On Arm Processor-PART-1: Arm Processor Multiple Choice Questions and Answers

MCQ On Arm Processor-PART-1 with answers and explanations for placement tests and job interviews. These solved Arm Processor MCQ are useful for the campus placement for all freshers including Engineering Students, MCA students, Computer and IT Engineers, etc.

Our Arm Processor MCQ- PART1 ( Arm Processor multiple Choice Questions ) focuses on the basic concept of the ARM processor. We will regularly update the quiz and most interesting thing is that questions come in a random sequence. So every time you will feel new questions.

We have already published a blog post that contains short questions related to embedded C. If you want you can also see this blog post. It would help you in your preparation. “Embedded  C Interview Questions”.

 

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Guideline of MCQ On Arm Processor:

This Arm Processor MCQ is intended for checking your knowledge of Arm Processor. It takes 1 hour to pass the Arm Processor MCQ. If you don’t finish the MCQ on Arm Processor within the mentioned time, all the unanswered questions will count as wrong. You can miss the questions by clicking the “Next” button and return to the previous questions by the “Previous” button. Every unanswered question will count as wrong. MCQ on Arm Processor has features of randomization which feel you a new question set at every attempt.

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MCQ On Arm Processor-PART-1

MCQ On Arm Processor- part 1

MCQ On Arm Processor-PART-1: Arm Processor Multiple Choice Questions and Answers

1 / 54

Application Program Status Register (APSR) access from?

2 / 54

What are the profiles for ARM architecture?

3 / 54

Memory can be accessed in ARM systems by __________ instructions.

4 / 54

The pseudo instruction used to load an address into the register is _________

5 / 54

Which among the following is/are integrated by OTG controller in order to implement OTG dual-role device functionality?

6 / 54

In CPU structure, where is one of the operands provided by an accumulator in order to store the result?

7 / 54

Which microcontrollers are adopted for designing medium-scale embedded systems?

8 / 54

How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

9 / 54

In the Cortex-R processor series, which among the following represent/s dual-core configuration along with the space-saving the floating-point unit?

10 / 54

The additional duplicate register used in ARM machines are called as _______

11 / 54

The benefits of using thumb instructions are as follows

12 / 54

____ is the processing of instruction broken down to smaller unit

13 / 54

Microprocessors have all of the following.

14 / 54

In Von Neumann architecture, which among the following handles all the operations of the system that are inside and outside the processor?

15 / 54

In the process of pipelining, which instructions are fetched from the memory by the ARM processor during the execution of current instruction?

16 / 54

In CPU structure, what kind of instruction to be executed is held by an Instruction Register (IR)?

17 / 54

ARM stands for _____________

18 / 54

Which types of an embedded system involve the coding at a simple level in an embedded 'C', without any necessity of RTOS?

19 / 54

In the branch instructions of ARM, what does the mnemonic BVC imply?

20 / 54

ARM processors where basically designed for _______

21 / 54

Which of the following statements are true with respect to pipelining.
I. Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is not visible to the programmer
II. Each step is called a pipe stage or pipe segment
III. Pipeline machine cycle is the time required to move an instruction one step down the pipeline

22 / 54

In the ARM, PC is implemented using ___________

23 / 54

An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is called _______.

24 / 54

Where the global variable stored?

25 / 54

In the SPI bus, which signal line carries data from master to slave device & hence regarded as Slave Input/Slave Data In (SI/SDI)?

26 / 54

The addressing mode where the EA of the operand is the contents of Rn is ______

27 / 54

Which type of branching instructions of thumb possesses 11-bit address & is generally applicable for slightly longer jumps in order to implement the instructions like GOTO of high-level languages?

28 / 54

While designing an embedded system, which sub-task-oriented process allocates the time steps for various modules that share similar resources?

29 / 54

Which type of handshake packet indicates that the device is incapable of accepting data as it is supposed to be busy with some other task?

30 / 54

The main importance of ARM microprocessors is providing operation with ______

31 / 54

RISC stands for _________

32 / 54

If the three stages of execution in pipelining are overlapped, how would be the speed of execution?

33 / 54

State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applied. This instruction branches to the initialization code.

34 / 54

How is the nature of instruction size in CISC processors?

35 / 54

Both baud rate and bit rate imply the same thing.

36 / 54

The ARM processors don’t support Byte addressability.

37 / 54

What is the capability of ARM7 f instruction for a second?

38 / 54

User Application will run in thread mode if any interrupt or exception event occurs, it will automatically enter in

39 / 54

The address system supported by ARM systems is/are ___________

40 / 54

Which parameter/s is/are included in the 'Time to market' design metric of an embedded system?

41 / 54

In the ARM Nomenclature ARMxTDMI, D and M stand for

42 / 54

The address space in ARM is ___________

43 / 54

Each instruction in ARM machines is encoded into __________ Word.

44 / 54

The offset used in the conditional branching is __________ bit.

45 / 54

ARM7 has an in-built debugging device?

46 / 54

What is/are the configuration status of the control unit in RISC Processors?

47 / 54

In the Cortex-A processor series, which among the following is the standalone and smallest processor in size constraints with high-end application support?

48 / 54

Which interrupt controller is present in the Cortex-A15 processor?

49 / 54

Is the ARM Cortex-M a microprocessor or a microcontroller?

50 / 54

If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

51 / 54

Which type of non-privileged processor mode is entered due to the raising of the high priority of an interrupt?

52 / 54

What 3 registers make up the Program Status Register (PSR)?

53 / 54

Abort mode generally enters when _______

54 / 54

24-bits equals how many bytes?

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