MCQ On Arm Processor-PART-1: Arm Processor Multiple Choice Questions and Answers

In the SPI bus, which signal line carries data from master to slave device & hence regarded as Slave Input/Slave Data In (SI/SDI)?

24-bits equals how many bytes?

The pseudo instruction used to load an address into the register is _________

Memory can be accessed in ARM systems by __________ instructions.

ARM stands for _____________

What 3 registers make up the Program Status Register (PSR)?

Application Program Status Register (APSR) access from?

What are the profiles for ARM architecture?

In the ARM, PC is implemented using ___________

The additional duplicate register used in ARM machines are called as _______

What is/are the configuration status of the control unit in RISC Processors?

Is the ARM Cortex-M a microprocessor or a microcontroller?

How is the nature of instruction size in CISC processors?

Which type of handshake packet indicates that the device is incapable of accepting data as it is supposed to be busy with some other task?

In the branch instructions of ARM, what does the mnemonic BVC imply?

Which types of an embedded system involve the coding at a simple level in an embedded 'C', without any necessity of RTOS?

Which interrupt controller is present in the Cortex-A15 processor?

In CPU structure, where is one of the operands provided by an accumulator in order to store the result?

The ARM processors don’t support Byte addressability.

In CPU structure, what kind of instruction to be executed is held by an Instruction Register (IR)?

ARM7 has an in-built debugging device?

In Von Neumann architecture, which among the following handles all the operations of the system that are inside and outside the processor?

In the Cortex-A processor series, which among the following is the standalone and smallest processor in size constraints with high-end application support?

Both baud rate and bit rate imply the same thing.

In the ARM Nomenclature ARMxTDMI, D and M stand for

The address space in ARM is ___________

____ is the processing of instruction broken down to smaller unit

Which type of non-privileged processor mode is entered due to the raising of the high priority of an interrupt?

The address system supported by ARM systems is/are ___________

Which microcontrollers are adopted for designing medium-scale embedded systems?

How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

Microprocessors have all of the following.

In the Cortex-R processor series, which among the following represent/s dual-core configuration along with the space-saving the floating-point unit?

Where the global variable stored?

Which of the following statements are true with respect to pipelining.
I. Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is not visible to the programmer
II. Each step is called a pipe stage or pipe segment
III. Pipeline machine cycle is the time required to move an instruction one step down the pipeline

The main importance of ARM microprocessors is providing operation with ______

Which among the following is/are integrated by OTG controller in order to implement OTG dual-role device functionality?

The benefits of using thumb instructions are as follows

What is the capability of ARM7 f instruction for a second?

If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is called _______.

RISC stands for _________

If the three stages of execution in pipelining are overlapped, how would be the speed of execution?

Abort mode generally enters when _______

While designing an embedded system, which sub-task-oriented process allocates the time steps for various modules that share similar resources?

Which parameter/s is/are included in the 'Time to market' design metric of an embedded system?

State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applied. This instruction branches to the initialization code.

ARM processors where basically designed for _______

In the process of pipelining, which instructions are fetched from the memory by the ARM processor during the execution of current instruction?

Each instruction in ARM machines is encoded into __________ Word.

The offset used in the conditional branching is __________ bit.

User Application will run in thread mode if any interrupt or exception event occurs, it will automatically enter in

The addressing mode where the EA of the operand is the contents of Rn is ______

Which type of branching instructions of thumb possesses 11-bit address & is generally applicable for slightly longer jumps in order to implement the instructions like GOTO of high-level languages?