ARM Cortex-M Thread Mode vs Handler Mode Explained

When working with ARM Cortex-M microcontrollers, understanding how the processor executes application code and responds to interrupts is very essential.

A Cortex-M processor spends most of its time executing application code. However, when an interrupt or another exception occurs, the processor must temporarily suspend its current execution, handle the event, and then resume the interrupted program.

But how does the processor distinguish between normal application execution and exception handling?

To manage these two types of execution, the ARM Cortex-M architecture provides two processor modes: Thread Mode and Handler Mode.

Thread Mode: Used to execute normal application code, including the main program and RTOS tasks.
Handler Mode: Used to execute exception handlers, including interrupt service routines (ISRs).

The processor enters Thread Mode after reset and switches to Handler Mode when an exception is taken. Once exception handling is complete, it can return to the interrupted execution context.

Understanding these modes is important because they influence how the processor handles interrupts, manages the stack, and controls access to system resources.

In this article, I will explain how Thread Mode and Handler Mode work, how the processor switches between them, and how to observe these transitions on an STM32 microcontroller using practical examples.

1. Thread Mode:

Thread Mode is the normal execution mode of the ARM Cortex-M processor. It is used to execute application code, including the main() function, application functions, and RTOS tasks.

After reset, the processor begins execution in Thread Mode. It first executes the startup code, which initializes the system and runtime environment before eventually transferring control to the application’s main() function.

Consider the following example:

int main()
{
    System_Init();

    while (1)
    {
        ReadSensor();
        ProcessData();
        UpdateOnDisplay();
    }
}

The above-mentioned application code executes in Thread Mode.

However, when an interrupt or another exception is accepted, the processor temporarily suspends the current execution and switches to Handler Mode to execute the corresponding exception handler.

An important characteristic of Thread Mode is that it can operate at either the privileged or unprivileged level. These are privilege levels, not separate execution modes.

Thread Mode can also use either the Main Stack Pointer (MSP) or the Process Stack Pointer (PSP), depending on the processor configuration.

Key characteristics of Thread Mode:

Used for normal application and RTOS task execution.
Can execute with privileged or unprivileged access.
Can use either MSP or PSP as its active stack pointer.
Can be interrupted by accepted exceptions.

2. Handler Mode:

Handler Mode is the execution mode used by the ARM Cortex-M processor to handle exceptions.

Whenever an exception is accepted, the processor automatically switches to Handler Mode and executes the corresponding exception handler.

Exceptions include:

Peripheral interrupts: UART, SPI, ADC, timer interrupts, and other external interrupt requests.
System exceptions: SysTick and Supervisor Call (SVC).
Fault exceptions: Memory Management Fault, BusFault, UsageFault, and HardFault, depending on the Cortex-M implementation.

Consider the following STM32 timer interrupt handler:

void TIM2_IRQHandler(void)
{
    if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET)
    {
        __HAL_TIM_CLEAR_FLAG(&htim2, TIM_FLAG_UPDATE);

        Timer_Event_Handler();
    }
}

When the TIM2 interrupt is accepted, the processor enters Handler Mode and executes TIM2_IRQHandler().

Unlike Thread Mode, Handler Mode always executes with privileged access and uses the Main Stack Pointer (MSP).

Handler Mode also supports nested exception handling. For example, a higher-priority interrupt can preempt a lower-priority interrupt handler, provided the applicable priority and interrupt-masking conditions allow it.

Key characteristics of Handler Mode:

Used to execute exception handlers and interrupt service routines (ISRs).
Always executes with privileged access.
Always uses MSP during handler execution.
Supports nested exception handling, subject to exception priorities and masking.
Returns from exception handling through the processor’s exception-return mechanism.

Thread Mode vs Handler Mode:

The following table summarizes the key architectural differences between Thread Mode and Handler Mode in ARM Cortex-M processors.

Feature	Thread Mode	Handler Mode
Purpose	Normal application execution	Exception handling
Entry	After reset or exception return to Thread Mode	When an exception is accepted
Privilege	Privileged or unprivileged	Always privileged
Stack pointer	MSP or PSP	Always MSP
Typical code	`main()`, application functions, RTOS tasks	ISRs, SysTick, SVC, and fault handlers
Exception preemption	Can be interrupted by accepted exceptions	Can be preempted by higher-priority exceptions

Note: Thread Mode and Handler Mode describe the processor’s execution modes, not whether the executing code is critical or non-critical. Thread Mode can execute either privileged or unprivileged application code, while Handler Mode always executes with privileged access.

How Does Processor Switch Between Thread and Handler Mode?

When a timer interrupt occurs, the Cortex-M processor switches from Thread Mode to Handler Mode to execute the interrupt handler. This transition is handled automatically by the exception mechanism.

The processor performs the following steps:

1. Exception Acceptance:

The NVIC manages interrupt requests, priorities, and pending states. When an exception becomes eligible for execution and the applicable priority and masking conditions permit it, the processor accepts the exception and initiates exception entry.

2. Automatic Context Stacking

Before executing the exception handler, the processor automatically saves the basic exception stack frame.

The basic stack frame contains eight 32-bit registers:

Register	Description
R0–R3	General-purpose registers
R12	General-purpose register
LR	Link Register
PC	Program Counter
xPSR	Program Status Register

These eight registers occupy 32 bytes in the basic exception stack frame.

The stack pointer used for saving the context depends on the interrupted execution mode:

Thread Mode using PSP: The exception stack frame is saved onto PSP.
Thread Mode using MSP: The exception stack frame is saved onto MSP.
Handler Mode: The exception stack frame is saved onto MSP.

3. Vector Table Lookup:

After saving the interrupted context, the processor obtains the address of the corresponding exception handler from the exception vector table.

4. Handler Execution

The processor enters Handler Mode and uses the Main Stack Pointer (MSP) as the active stack pointer.

The processor then executes the corresponding exception handler.

During exception entry, the Link Register (LR) receives a special value called EXC_RETURN, which provides information about how the processor should return from the exception.

5. Exception Return

When the exception handler completes, the processor uses the EXC_RETURN value to determine how to restore the interrupted execution context.

It restores the previously stacked registers and resumes execution in the appropriate mode:

Thread Mode, if the exception interrupted Thread Mode.
Handler Mode, if the exception interrupted another Handler Mode.